Sierra Video VS User Manual download pdf (Page 51)

Tahoe Series 16

The matrix interface has special timing requirements. These time delays are too long to

be provided by the MC68302 wait state or DTACK generator. This special timing is

generated externally using U14, U15, and U12.

The basic operation of the circuit is U14, which counts up to 32 starting from 0 whenever

a CS3 cycle is initiated. At this count it returns DTACK to the MC68302 which terminates

the memory cycle.

U14 is a 74F579 binary counter being clocked by CLKO at a 60 nanosecond rate. It is

held in permanent reset (count = 0) whenever CS3 is high.(U15 provides an inverter to

keep the counter reset). As soon as CS3 falls low, indicating an access to any of the 4

peripherals in this memory area, U14 begins counting up. U14 continues counting up until

it reaches a count of 8, at which point the output of U15-6 goes high because U15-4 is

high but U15-5 is low. U14 continues counting until it reaches a count of 16, at which

point U15-5 is high, but U15-4 is now low, so U15-6 is still high. Eventually U14 reaches

a count of 24, at which point both pin 4 and pin 5 of U15 are high, so the output falls low.

The net effect of this is to generate a strobe enable signal to the matrix which lasts for

approximately 860 nanoseconds. This strobe enable signal is fed into U7, which decodes

which of the 8 levels of strobe are desired based on the setting of address lines A6, A7,

and A8. But U14 has not yet finished counting; in fact the memory access to this region is

not terminated until DTACK has been recognized by the processor. U14 continues

counting until it reaches a count of 32, whereupon it drives U15-10 high, which becomes

inverted, and drives U12-19 low, which asserts the DTACK signal to the processor.

Within several clock periods the MC68302 recognizes the DTACK and terminates the

memory cycle. It removes CS3 assertion, which immediately returns U14 to the held-in-

reset-count state. U14 returns to 0, and the entire process can then repeat with another

memory cycle.

Because 8 clocks are provided at the start of each cycle before the matrix strobe is

asserted, a 480 nanosecond leading-edge delay is provided for data setup. The strobe

signal lasts almost 900 nanoseconds, and is followed by another 480 nanosecond delay

during which the data remains stable. After this 1.8 microsecond, the cycle is complete

and could begin again.

Matrix Interface

The routing switcher interface consists of three parallel groups of lines; input select, bus

select and strobe(s).

U5 latches the D0 through D7 processor lines during each matrix interface cycle. This

provides selection capability of up to 256 inputs. At the same time U6 latches address

lines A0 through A7. This provides control of up to 256 output buses.

The input select and bus select data is asserted for a total of 1800 ns. During the first 600

ns of this time the strobe lines are all low. During the second 600 ns period one strobe is

asserted high. During the final 600 ns all the strobe outputs are low again.

For each crosspoint that must be set, the above cycle is repeated. After the MC68302

receives a vertical interrupt, only those crosspoints in the matrix whose state must be

changed since the last verticle interrupt are changed. When no new changes are required

the outputs of U5, U6, and U7 remain static.

Vertical interrupt occurs at line 6 (for NTSC or line 3 for PAL). The processor can output

32 crosspoint changes per 64 microsecond TV line. A 256 output system can be entirely

reconfigured by line 14, well before the beginning of the active picture.

Vertical Interrupt Generator

Sync, video black or any composite video source can be used as a locking input to the

504001 module. The signal is AC coupled to Q2, an emitter follower. Q2 provides a low

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Sierra Video VS User Manual Page 51

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